XC95108 VHDL LED Blinking

The XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of six 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. It has a 5V in-system programmable (ISP) that allow us to program/erase up to 10000 cycles.

The XC9572 XC95108 Prototype Board

XC95108 Architecture

We can design the circuit using schematic tool, VHLD, or Verilog using Xilinx ISE. The ISP tool could be a legacy parallel port cable (II) or even a modern USB JTAG.

In this introductory example, I design a frequency divider circuit using VHDL. The frequency source is driven from a 25.175MHz crystal oscillator. The output frequency is 1Hz that will drive an output LED.

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-- Company: 
-- Engineer: 
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-- Create Date:    13:53:19 01/23/2024 
-- Design Name: 
-- Module Name:    led_blink - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity led_blink is
	 Generic ( FREQ : INTEGER :=25175000;
		   FREQ_H: INTEGER :=12587500);
    Port ( CLK : in  STD_LOGIC;
           LED : out  STD_LOGIC);
end led_blink;
 
architecture Behavioral of led_blink is
	SIGNAL TOGGLE: STD_LOGIC;
begin
 
LED<=TOGGLE;
 
PROCESS(CLK)
	VARIABLE COUNTER: INTEGER RANGE 0 TO FREQ;
 
BEGIN
	if(CLK'EVENT AND CLK='1') THEN COUNTER:=COUNTER+1; END IF;
	if(COUNTER>=FREQ_H) THEN 
		TOGGLE<= TOGGLE XOR '1'; 
		COUNTER:=0; 
	END IF;
 
END PROCESS;
 
end Behavioral;
 
 

I use VHDL Generic to parameterize the design, conferring the code more flexibility and flexibility.

This VHDL code could fit an XC9572 CPLD. But this chip is not currently available at my workshop.

XC95108 PLCC-84

I use an XC95108 PC84 (PLCC-84) with socket. Its speed grade is 20 Nano seconds.

Xilinx Impact ISP

I still use the Xilinx Parallel Cable III to program this old CPLD. Its operating speed is slower than a modern USB JTAG.

Click here to download this VHDL example.