XC95108 VHDL Parallel to Serial Shift Registers and Arduino Example

A parallel to serial shift register is useful for microprocessor digital inputs extending. For instant a keypad input for printer for photocopier machine. There are many off-the-shelf parallel to serial shift register chips, especially the SN74HC165.

Hardware Testing

Using a programmable logic device we can design this kind of chip with customizable operations, and the numbers of I/O. This job could be done with a CPLD chip and its design tool, VHLD, Verilog code, or even schematic design tool.

Running Arduino Program and the XC95108

In this example, I use an XC95108 CPLD to design a parallel to serial converter chip. VHDL code is preferred for this design. This design contains,

• Clock (CLK) input,
• LOAD input to latch data from an 8-bit digital input to the internal register,
• Serial Data Out (DOUT) that shift data serially at the rising edge of input clock,
• Digital Input (D) is an 8-bit data input.

The overall process requires 9 clock cycles. At the first clock, data will be read and latched into an internal register, then the 8-bit serial data shifting out will be processed.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:31:41 02/03/2024 
-- Design Name: 
-- Module Name:    parallel_serial_2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity parallel_serial_2 is
    Port ( CLK : in  STD_LOGIC;
           LOAD : in  STD_LOGIC;
           DOUT : out  STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (7 downto 0));
end parallel_serial_2;
 
architecture Behavioral of parallel_serial_2 is
	SIGNAL REG: STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
	PROCESS(CLK,LOAD)
		BEGIN
			IF(CLK'EVENT AND CLK='1') THEN
				IF(LOAD='1') THEN REG<=D;
				ELSE REG<=REG(6 DOWNTO 0)&'0'; END IF;
			END IF;
	END PROCESS;
	DOUT<=REG(7);
end Behavioral;
 
 

You can use the FloorPlan I/O tool in the ISE Design Suite to assign its I/O pins. On the XC95108 CPLD Prototype Board, I set the I/O as follow.

#PACE: Start of Constraints generated by PACE
 
#PACE: Start of PACE I/O Pin Assignments
NET "CLK"  LOC = "P50"  ;
NET "D<0>"  LOC = "P48"  ;
NET "D<1>"  LOC = "P47"  ;
NET "D<2>"  LOC = "P46"  ;
NET "D<3>"  LOC = "P45"  ;
NET "D<4>"  LOC = "P44"  ;
NET "D<5>"  LOC = "P43"  ;
NET "D<6>"  LOC = "P41"  ;
NET "D<7>"  LOC = "P40"  ;
NET "DOUT"  LOC = "P52"  ;
NET "LOAD"  LOC = "P51"  ;
#PACE: Start of PACE Area Constraints
 
#PACE: Start of PACE Prohibit Constraints
 
#PACE: End of Constraints generated by PACE
 

The Arduino is very popular for most of electronics projects. I use an Arduino Uno to read the data from this chip.

 
 
const char clockPin= 13;
const char Enable = 10;
const char dataPin=12;
 
uint8_t incoming=0,oldData;
 
void setup() {
  Serial.begin(9600);
  Serial.println("Arduino ShiftIn And XC95108 Parallel To Serial Converter.");
  pinMode(clockPin,OUTPUT);
  pinMode(Enable,OUTPUT);
  pinMode(dataPin,INPUT);
  digitalWrite(clockPin,LOW);
  digitalWrite(Enable,LOW);
}
 
void loop() {
  digitalWrite(Enable,HIGH);
  digitalWrite(clockPin,LOW);
  digitalWrite(clockPin,HIGH);
  digitalWrite(Enable,LOW);
 
  for(uint8_t i=0;i<8;i++){
    digitalWrite(clockPin,LOW);
    if(digitalRead(dataPin)==1) incoming|=(1<<(7-i));
    else incoming&=~(1<<(7-i));   
    digitalWrite(clockPin,HIGH);
  }
  if(incoming!=oldData){
    Serial.println("Received 8-Bit HEX Data: 0x" + String(incoming,HEX));
    Serial.println("Received 8-Bit BIN Data: 0b" + String(incoming,BIN));
    oldData=incoming;
  }
  // Serial.println(incoming,HEX);
  //Serial.println(incoming,BIN);
  delay(1500);
}

Click here to download this example.

XC95108 Two-Digit 7-Segment Shift Registers VHDL Example

In previous post, I use the XC95108 to make a 16-bit LED shift registers. It's similar to the SNHC164 serial in parallel out shift registers chip. Using a CPLD and VHDL code we can customize any digital circuit. 

The Arduino Uno and the XC95108 CPLD Prototype Board 

Here I make another serial in parallel out shift registers chip that's similar to the SN74HC595. It's a two-digit 7-Segment display driver with SPI interface. It has the following I/O:

• Reset (RST) input (active low)
• Enable (EN) input for data latching
• Serial Data In (MOSI)
• Serial Clock In (SCK)
• 7-Segment Digit 1 (LEDA)
• and 7-Segment Digit 2 (LEDB).

The 7-Segment display is a two-digit 0.56" red common cathode display. The shift registers process is synchronize with the logic high level of serial clock input (SCK). Shift registers data are latched into the output LED ports at the high to low transition of the EN (Enable) pin.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:29:52 01/30/2024 
-- Design Name: 
-- Module Name:    spi_7_2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity spi_7_2 is
    Port ( RST : in  STD_LOGIC;
           EN : in  STD_LOGIC;
           SCK : in  STD_LOGIC;
           MISO : in  STD_LOGIC;
           LEDA : out  STD_LOGIC_VECTOR (7 downto 0);
           LEDB : out  STD_LOGIC_VECTOR (7 downto 0));
end spi_7_2;
 
architecture Behavioral of spi_7_2 is
	SIGNAL REGA,REGB: STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
PROCESS(SCK,RST,EN)
	BEGIN
		IF(RST='0') THEN REGA<=x"00"; REGB<=x"00";
		ELSIF(SCK'EVENT AND SCK='1') THEN
			-- REGISTER A
			REGA(0)<=MISO;
			REGA(1)<=REGA(0);
			REGA(2)<=REGA(1);
			REGA(3)<=REGA(2);
			REGA(4)<=REGA(3);
			REGA(5)<=REGA(4);
			REGA(6)<=REGA(5);
			REGA(7)<=REGA(6);
 
			-- REGISTER B
			REGB(0)<=REGA(7);
			REGB(1)<=REGB(0);
			REGB(2)<=REGB(1);
			REGB(3)<=REGB(2);
			REGB(4)<=REGB(3);
			REGB(5)<=REGB(4);
			REGB(6)<=REGB(5);
			REGB(7)<=REGB(6);
 
		END IF;
		-- INPUT DATA LATCH
		IF(EN'EVENT AND EN='1') THEN
		LEDA<=REGA; LEDB<=REGB;
		END IF;
END PROCESS;
 
end Behavioral;
 
 

This VHDL circuit design uses 32 macro cells and 27 function blocks.

XC95108 CPLD Reports

I connect the CPLD to its on-board I/O devices (user constraint file) as follow. 

#PACE: Start of Constraints generated by PACE
 
#PACE: Start of PACE I/O Pin Assignments
NET "EN"  LOC = "P54"  ;
NET "LEDA<0>"  LOC = "P23"  ;
NET "LEDA<1>"  LOC = "P24"  ;
NET "LEDA<2>"  LOC = "P36"  ;
NET "LEDA<3>"  LOC = "P34"  ;
NET "LEDA<4>"  LOC = "P33"  ;
NET "LEDA<5>"  LOC = "P21"  ;
NET "LEDA<6>"  LOC = "P35"  ;
NET "LEDA<7>"  LOC = "P37"  ;
NET "LEDB<0>"  LOC = "P19"  ;
NET "LEDB<1>"  LOC = "P20"  ;
NET "LEDB<2>"  LOC = "P31"  ;
NET "LEDB<3>"  LOC = "P25"  ;
NET "LEDB<4>"  LOC = "P26"  ;
NET "LEDB<5>"  LOC = "P17"  ;
NET "LEDB<6>"  LOC = "P18"  ;
NET "LEDB<7>"  LOC = "P32"  ;
NET "MISO"  LOC = "P53"  ;
NET "RST"  LOC = "P50"  ;
NET "SCK"  LOC = "P52"  ;
 
#PACE: Start of PACE Area Constraints
 
#PACE: Start of PACE Prohibit Constraints
 
#PACE: End of Constraints generated by PACE
 

Using the Arduino Uno is common for most of electronics hobbyists. I use the Arduino SPI to send 7-Segment data to the XC95108 CPLD Prototype Board. This program will count up and down between 0 and 99.

#include <SPI.h>
 
const char data_7[]={0x3F,0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x6F};
const char EN=10;
volatile char data[2];
volatile char count=0,up_down=0;
 
void setup() {
  SPI.begin();
  pinMode(EN,OUTPUT);
  digitalWrite(EN,LOW);
}
 
void loop() {
  data[1]=data_7[count%10];  
  data[0]=data_7[count/10];
  SPI.transfer(data,2);
  digitalWrite(EN,HIGH);
  delay(1);
  digitalWrite(EN,LOW);
  if(count==99) up_down=1;
  else if(count==0) up_down=0;
  if(up_down==1) count--;
  else if(up_down==0) count++;
  delay(250);
}

The Arduino Uno must connects to the CPLD as follow.

• Arduino Uno GND              -> XC95108 CPLD GND
• Arduino Uno SCK (PIN13)   -> XC95108 CPLD (P52)
• Arduino Uno MOSI (PIN11) -> XC95108 CPLD (P53)
• Arduino Uno EN (PIN10)     -> XC95108 CPLD (P54)

Click here to download its source file.

XC95108 16-bit Serial In Parallel Out Shift Registers VHDL Example

A Serial-In-Parallel-Out shift register IC is very popular among micro-controller programmers. It's commonly use for I/O extending, LED driving, relay driving, etc. The SN75C595N or the SN74HC164 are commonly used with micro-controllers to expand their outputs.

Hardware test on bread-board with Arduino Uno SPI

Using a CPLD/FPGA we can create any digital circuit including this type shift registers chip. In this example, I use the XC95108 CPLD to create a 16-bit serial in parallel out shift registers chip. The chosen language is VHDL.

The designed chip include reset(RST), serial clock(CLK), and serial data in (DIN). Its output is an 16-bit output port connects to LED.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:34:09 01/29/2024 
-- Design Name: 
-- Module Name:    shift_regs_16_LED - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity shift_regs_16_LED is
    Port ( CLK : in  STD_LOGIC;
           RST : in  STD_LOGIC;
           DIN : in  STD_LOGIC;
           LEDS : out  STD_LOGIC_VECTOR (15 downto 0));
end shift_regs_16_LED;
 
architecture Behavioral of shift_regs_16_LED is
	SIGNAL REGS: STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
PROCESS(CLK,RST)
	BEGIN
		IF(RST='0') THEN REGS<=x"0000";
		ELSIF(CLK'EVENT AND CLK='1') THEN
			REGS(0)<=DIN;
			REGS(1)<=REGS(0);
			REGS(2)<=REGS(1);
			REGS(3)<=REGS(2);
			REGS(4)<=REGS(3);
			REGS(5)<=REGS(4);
			REGS(6)<=REGS(5);
			REGS(7)<=REGS(6);
			REGS(8)<=REGS(7);
			REGS(9)<=REGS(8);
			REGS(10)<=REGS(9);
			REGS(11)<=REGS(10);
			REGS(12)<=REGS(11);
			REGS(13)<=REGS(12);
			REGS(14)<=REGS(13);
			REGS(15)<=REGS(14);
		END IF;
		LEDS<=REGS;
END PROCESS;
 
end Behavioral;
 
 

Its internal circuit doesn't need additional clock input to synchronize input data. The data is synchronized with serial clock pin from external device.

Its I/O pins are assigned as follow using the Floorplan I/O tool.

#PACE: Start of Constraints generated by PACE
 
#PACE: Start of PACE I/O Pin Assignments
NET "CLK"  LOC = "P48"  ;
NET "DIN"  LOC = "P50"  ;
NET "LEDS<0>"  LOC = "P63"  ;
NET "LEDS<10>"  LOC = "P67"  ;
NET "LEDS<11>"  LOC = "P68"  ;
NET "LEDS<12>"  LOC = "P69"  ;
NET "LEDS<13>"  LOC = "P70"  ;
NET "LEDS<14>"  LOC = "P71"  ;
NET "LEDS<15>"  LOC = "P72"  ;
NET "LEDS<1>"  LOC = "P62"  ;
NET "LEDS<2>"  LOC = "P61"  ;
NET "LEDS<3>"  LOC = "P58"  ;
NET "LEDS<4>"  LOC = "P57"  ;
NET "LEDS<5>"  LOC = "P56"  ;
NET "LEDS<6>"  LOC = "P55"  ;
NET "LEDS<7>"  LOC = "P54"  ;
NET "LEDS<8>"  LOC = "P65"  ;
NET "LEDS<9>"  LOC = "P66"  ;
NET "RST"  LOC = "P47"  ;
 
#PACE: Start of PACE Area Constraints
 
#PACE: Start of PACE Prohibit Constraints
 
#PACE: End of Constraints generated by PACE
 

After the design and programming process are completed, we can test this circuit manually with a few on-board input switches. For convenience we can use a popular Arduino Uno as an SPI master device transferring a 16-bit data to this shift registers chip.

#include<SPI.h>
 
void setup() {
  SPI.begin();
}
 
char data[2];
void loop() {
  data[0]=0xF0;
  data[1]=0x0F;
  SPI.transfer(data,2);
  delay(1000);
  data[0]=0x0F;
  data[1]=0xF0;
  SPI.transfer(data,2);
  delay(1000);
}

The circuit connections between the Arduino Uno and the XC95108 CPLD are:

Arduino Uno            XC95108 CPLD Prototype Board

GND                        GND

PIN11 (MOSI)            P50

PIN13 (SCK)               P48

I use the Arduino SPI module and library without bit-banging. Optionally we can use the on-board 7-Segment display instead of the LED.

Click here to download its source file.