XC95108 Rotates LED Example using VHDL

The VHDL Rotate Left (ROL) and Rotate Right (ROR) with carry operators are used for shifting the data left or right with a specific position. Unlike the VHDL Shift operators, it has carry bit. These operators are useful for serial data transmitting or receiving. 

XC95108 Hardware Testing

In this example, I use these operators to make a simple LED chasing circuit. I created two digital output port, PORTA and PORTB. These two ports rotates their output bits in an opposite direction.

XC95108 CPLD and LED Schematic

The shifting rate is 100 Millis seconds. I use a clock divider circuit that divide a 25.175MHz signal source to a 100Hz clock frequency.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:44:09 01/24/2024 
-- Design Name: 
-- Module Name:    led_shift - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity led_shift is
	 Generic ( FREQ : INTEGER :=25175000;
		   FREQ_H: INTEGER :=12587500);
    Port ( PORTA : out  BIT_VECTOR (7 downto 0);
           PORTB : out  BIT_VECTOR (7 downto 0);
           CLK : in  STD_LOGIC);
end led_shift;
 
architecture Behavioral of led_shift is
	SIGNAL RA,RB: BIT_VECTOR(7 DOWNTO 0):=X"01";
 
begin
 
PROCESS(CLK)
	VARIABLE COUNTER: INTEGER RANGE 0 TO 2517500;
 
	BEGIN
	IF(CLK'EVENT AND CLK='1') THEN 
		COUNTER:=COUNTER+1; 
		IF(COUNTER=2517500) THEN 
			RA<=RA ROR 1; 
			RB<=RB ROL 1; 		
		END IF;
	END IF;
 
	PORTA<=RA;
	PORTB<=RB;
END PROCESS;
 
end Behavioral;
 
 

This digital circuit needs about 28 macro cells and 86 input function block of the XC95108 CPLD.

XC95108 CPLD Reports

The user constraints for I/O pins selection is listed below.

#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "CLK"  LOC = "P9"  ;
NET "PORTA<0>"  LOC = "P63"  ;
NET "PORTA<1>"  LOC = "P62"  ;
NET "PORTA<2>"  LOC = "P61"  ;
NET "PORTA<3>"  LOC = "P58"  ;
NET "PORTA<4>"  LOC = "P57"  ;
NET "PORTA<5>"  LOC = "P56"  ;
NET "PORTA<6>"  LOC = "P55"  ;
NET "PORTA<7>"  LOC = "P54"  ;
NET "PORTB<0>"  LOC = "P65"  ;
NET "PORTB<1>"  LOC = "P66"  ;
NET "PORTB<2>"  LOC = "P67"  ;
NET "PORTB<3>"  LOC = "P68"  ;
NET "PORTB<4>"  LOC = "P69"  ;
NET "PORTB<5>"  LOC = "P70"  ;
NET "PORTB<6>"  LOC = "P71"  ;
NET "PORTB<7>"  LOC = "P72"  ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

The XC9572 can be used in this simple circuit. I use the Xilinx ISE Design 14.7 running on Windows 10. The Xilinx Parallel Cable III still work very nice in this Xilinx ISE version. Click here to download its source file.