In this VHDL example, I use an XC85108 CPLD to read an 8-bit binary input. Then the internal digital circuit will convert it into hexadecimal value. The result is in 2 place values hexadecimal displaying on a two-digit common cathode 7-Segment display.
XC95108 CPLD DIY Prototype Board |
I divided the 8-bit input into two nibble, the higher nibble and the lower nibble. The VHDL conversion between these two bases is very straight forward. The code just decode these two nibble using the concurrent VHDL WITH and Select statement.
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:14:12 01/25/2024 -- Design Name: -- Module Name: bin_8_to_hex - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity bin_8_to_hex is Port ( BIN_H, BIN_L : in STD_LOGIC_VECTOR (3 downto 0); LED1 : out STD_LOGIC_VECTOR (7 downto 0); LED2 : out STD_LOGIC_VECTOR (7 downto 0)); end bin_8_to_hex; architecture Behavioral of bin_8_to_hex is begin --LOWER NIBBLE WITH BIN_L SELECT LED1 <= x"3F" WHEN x"0", x"06" WHEN x"1", x"5B" WHEN x"2", x"4F" WHEN x"3", x"66" WHEN x"4", x"6D" WHEN x"5", x"7D" WHEN x"6", x"07" WHEN x"7", x"7F" WHEN x"8", x"6F" WHEN x"9", x"77" WHEN x"A", x"7C" WHEN x"B", x"39" WHEN x"C", x"5E" WHEN x"D", x"79" WHEN x"E", x"71" WHEN x"F", x"00" WHEN OTHERS; --HIGHER NIBBLE WITH BIN_H SELECT LED2 <= x"3F" WHEN x"0", x"06" WHEN x"1", x"5B" WHEN x"2", x"4F" WHEN x"3", x"66" WHEN x"4", x"6D" WHEN x"5", x"7D" WHEN x"6", x"07" WHEN x"7", x"7F" WHEN x"8", x"6F" WHEN x"9", x"77" WHEN x"A", x"7C" WHEN x"B", x"39" WHEN x"C", x"5E" WHEN x"D", x"79" WHEN x"E", x"71" WHEN x"F", x"00" WHEN OTHERS; end Behavioral;
The XC95108, 7-Segment display and input switch wiring diagram are listed below.
Wiring Diagram on the XC95108 CPLD Prototype Board |
In Xilinx ISE we need to assign its I/O pins using Floorplan IO tool.
XC9500 CPLD Report |
This digital circuit design requires very little resource of the XC95108 CPLD. We can use the Xilinx Parallel Cable III to program this CPLD in Xilinx ISE 14.7.
Click here to download this example.
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