XC9536 Switch And LED Interfacing With Delay Using VHDL

Overview

In this VHDL example, I use an input push button to toggle an output LED. It also has a delay circuit that created by frequency divider. Signal source is generated by the on-board 60Hz NE555 square wave oscillator. 

On-Board Testing

In VHDL It requires two I/O pin,

1. LED - Output direction with STD_LOGIC type. It's assigned to pin 35 of XC9536 CPLD, connecting the on-board output LED.
2. CLK - Input direction with STD_LOGIC type. It's assigned to pin 5 (GCK1) of XC9536 CPLD.
3. BUTTON : Input direction STD_LOGIC type. It's assigned to pin 19, connecting to the on-board pulled up tactile switch. It's an active low signal.

A counter variable "count" holds a numeric value up to 60 counts. It's necessary for sequential circuit inside the process. A toggle signal with STD_LOGIC type is added for signal assignment to LED I/O pin. When a low to high clock pulse is activated at clock pin (CLK) it increases its content 1 time. Whenever it reaches 30 counts and the the input button "BUTTON" is pressed, it will be reset to 0. And the toggle signal will change its logic state. The LED logic state depends on the toggle signal.

VHDL Code

The VHDL code contains a dozen line of statements. Only one process evaluates the input and output. This process requires one sensitive parameter "CLK" in its list.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:49:59 12/05/2023 
-- Design Name: 
-- Module Name:    Toggle_LED_CLK - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Toggle_LED_CLK is
    Port ( LED : out  STD_LOGIC;
			  CLK	: in STD_LOGIC;	
           BUTTON : in  STD_LOGIC);
end Toggle_LED_CLK;
 
architecture Behavioral of Toggle_LED_CLK is
 
signal	toggle: STD_LOGIC;
 
begin
 
PROCESS (CLK)
variable count	: INTEGER RANGE 0 TO 59;
 
BEGIN
if(CLK'EVENT AND CLK = '1') THEN
	count := count + 1;
	if(count>=30 AND BUTTON = '0') then
		toggle <= toggle XOR '1';
		count := 0;
		LED <= toggle;
	end if;
end if;
end process;
end Behavioral;
 
 

Click here to download its source file. I want to know its RTL(Register Transfer Level) schematic.

Register Transfer Level (RTL)

User Constraints

I don't use VHDL simulation here. This circuit will be constructed on an XC9536 CPLD using my test board. So I need to select the I/O pins before the program file is uploaded to CPLD.

Expand the User Constraints, and double click on the Floorplan IO to assign its I/O pins. And then save the document before we close it.

I/O Pins Assignment

A user constraints file ".ucf" will be generated.

#PACE: Start of Constraints generated by PACE
 
#PACE: Start of PACE I/O Pin Assignments
NET "BUTTON"  LOC = "P19"  ;
NET "CLK"  LOC = "P5"  ;
NET "LED"  LOC = "P35"  ;
 
#PACE: Start of PACE Area Constraints
 
#PACE: Start of PACE Prohibit Constraints
 
#PACE: End of Constraints generated by PACE

After it's completed, we need to run the Implement Design to generated its program file ".jed". This file will be selected to program the target CPLD device.

Cable Set Up - Select Parallel Cable III

I use the legacy parallel port interface connects to Parallel Cable III JTAG cable to program the target device. I use ISE Design Suites 14.7 running on Windows 10. My HP MT-6300 Desktop PC with parallel port still support this legacy I/O port. If you need a modern high speed USB JTAG, it works better than this old one's.

Programming 

Using this parallel port cable we need to be patient because of its low speed, and cable connection error.