XC9536 CPLD Simple Three-Digit Multiplexing Display Using VHDL

In this VHDL Example, an XC9536 CPLD drives a 3-digit common cathode multiplexing display. It requires a square signal generator for display timing. The generator frequency is 60Hz generated by an on-board NE555 square wave oscillator. Each digits are activated for 16 milliseconds.

XC9536 Prototyping Board 

VHDL codes for this example is very simple. We directly assign 7-segment data to each digits. However we can use VHDL array data type.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:41:42 12/11/2023 
-- Design Name: 
-- Module Name:    mux_3 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity mux_3 is
    Port ( CLK : in  STD_LOGIC;
           COM : out  STD_LOGIC_VECTOR (2 downto 0);
           DAT : out  STD_LOGIC_VECTOR (7 downto 0));
end mux_3;
 
architecture Behavioral of mux_3 is
 
begin
process(CLK)
	variable	count	:	INTEGER	RANGE	0	TO	2;
	begin
		if(CLK'EVENT AND CLK='1') then	count:=count+1;	end if;
		CASE	count	IS
			WHEN	0	=>
				DAT<=x"06";	COM<="001";
			WHEN	1	=>
				DAT<=x"5B";	COM<="010";
			WHEN	2	=>
				DAT<=x"4F";	COM<="100";
			WHEN	OTHERS	=>	NULL;
		END CASE;
end process;
 
 
 
end Behavioral;
 
 

All 7-Segment data pins share with the on-board output LEDs. So it reduce driving current. I use an ULN2003 transistors array to drive each common pins.

I assign all output pins in Xilinx PACE as follow.

Pin Assignments

Click here to download its source file.

If you are a beginner in VHDL you can watch this video to see the overall process.