XC9536 CPLD 8-Bit Serial In Parallel Out Shift Registers using VHDL

Overview

A serial in parallel out shift registers is very useful for I/O expanding. For instance, they can use it for driving multiple seven segments display, a dot matrix display, multiple output relays, etc. Standard serial-in-parallel-out shift registers ICs usage are the SN74HC595 and SN74HC164. They are very easy to find at very low cost. The controller uses only a few output pins to control these chips.

A 4-Digit Common Anode SN74HC595N Serial Display

In this example, I designed an 8-bit serial-in-parallel-out shift registers using an XC9536 CPLD. All components are already placed on board. Its inputs outputs are listed below,

1. Reset
2. Clock
3. Data
4. Output

There's no output enable signal, or a 8th bit output for cascading. This circuit receive the least significant bit (LSB) first. So it shifts from left to right.

XC9536 Prototyping Board

VHDL Code

Its VHDL code is quite simple. I added one 8-bit signal to process serial data reception. This design a sequential process.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:36:04 12/11/2023 
-- Design Name: 
-- Module Name:    shift_registers_8 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity shift_registers_8 is
    Port ( RST : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           DAT : in  STD_LOGIC;
           D : out  STD_LOGIC_VECTOR (7 downto 0));
end shift_registers_8;
 
architecture Behavioral of shift_registers_8 is
signal	Q	:	STD_LOGIC_VECTOR(7 DOWNTO 0);
 
begin
 
process(CLK,RST)
	begin
		if(RST='0') then	Q<=x"00";
		elsif(CLK'EVENT AND CLK='0') then
			Q(0)<=DAT;
			Q(1)<=Q(0);
			Q(2)<=Q(1);
			Q(3)<=Q(2);
			Q(4)<=Q(3);
			Q(5)<=Q(4);
			Q(6)<=Q(5);
			Q(7)<=Q(6);
		end if;
		D<=Q;
end process;
 
end Behavioral;
 
 

Pin Assignments

I use the Xilinx PACE Tool to set its I/O pins as follow.

Xilinx PACE

After we save and close this windows, a user constraint file will be created.

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments

NET "CLK"  LOC = "P19"  ;

NET "D<0>"  LOC = "P33"  ;

NET "D<1>"  LOC = "P34"  ;

NET "D<2>"  LOC = "P35"  ;

NET "D<3>"  LOC = "P36"  ;

NET "D<4>"  LOC = "P37"  ;

NET "D<5>"  LOC = "P38"  ;

NET "D<6>"  LOC = "P39"  ;

NET "D<7>"  LOC = "P40"  ;

NET "DAT"  LOC = "P25"  ;

NET "RST"  LOC = "P18"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Device Programming

A parallel port JTAG cable is preferred since I write this code on a desktop computer that has an LPT-25 connector.

Device Programming Using Xilinx Parallel Cable III JTAG

Click here to download its source file.