A timer high ladder diagram instruction Thi creates a high time output delay whenever its input changes from low to high. The high time delay is set in its property.
Its timing diagram shown below.
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| Timer high instruction timing diagram |
Duration of its input high must greater than the PLC cycle time. The duration of high time delay could be adjusted.
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| Timer high delay property |
An introductory example use an input contact to activate this timer. When it's true, this time output a high time duration of 5 minutes before it reset.
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| Timer high introductory example |
Click here to download this introductory example.
This example use a negate type input contact.
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| Timer high example using a negate input contact |
Click here to download this the ladder diagram for this example.
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