XC9536 CPLD Simple Three-Digit Multiplexing Display Using VHDL

In this VHDL Example, an XC9536 CPLD drives a 3-digit common cathode multiplexing display. It requires a square signal generator for display timing. The generator frequency is 60Hz generated by an on-board NE555 square wave oscillator. Each digits are activated for 16 milliseconds.

XC9536 Prototyping Board 

VHDL codes for this example is very simple. We directly assign 7-segment data to each digits. However we can use VHDL array data type.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:41:42 12/11/2023 
-- Design Name: 
-- Module Name:    mux_3 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity mux_3 is
    Port ( CLK : in  STD_LOGIC;
           COM : out  STD_LOGIC_VECTOR (2 downto 0);
           DAT : out  STD_LOGIC_VECTOR (7 downto 0));
end mux_3;
 
architecture Behavioral of mux_3 is
 
begin
process(CLK)
	variable	count	:	INTEGER	RANGE	0	TO	2;
	begin
		if(CLK'EVENT AND CLK='1') then	count:=count+1;	end if;
		CASE	count	IS
			WHEN	0	=>
				DAT<=x"06";	COM<="001";
			WHEN	1	=>
				DAT<=x"5B";	COM<="010";
			WHEN	2	=>
				DAT<=x"4F";	COM<="100";
			WHEN	OTHERS	=>	NULL;
		END CASE;
end process;
 
 
 
end Behavioral;
 
 

All 7-Segment data pins share with the on-board output LEDs. So it reduce driving current. I use an ULN2003 transistors array to drive each common pins.

I assign all output pins in Xilinx PACE as follow.

Pin Assignments

Click here to download its source file.

If you are a beginner in VHDL you can watch this video to see the overall process.

XC9536 CPLD Ring Counter Example Using VHDL

A digital electronics ring counter chip is popular for electronics hobbyists especially in a DIY LED chasing circuit. A common digital IC ring counter is the CD4017. It's easily to find with a very low price.

Ring Counter Testing On XC9536 CPLD Board

A Ring Counter Board Using CD4017 And NE555 Oscillator

However we can use a programmable logic device to design a simple ring counter circuit. A small CPLD "XC9536" can do this job. I use VHDL to build a ring counter. We can customize a number of outputs and its operating modes.

I use clock and clear input signal. The output is an 8-bit standard logic vector. Input clock is driven from a 60Hz on-board NE555 square signal generator.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    07:53:59 12/08/2023 
-- Design Name: 
-- Module Name:    ring_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ring_counter is
    Port ( CLK : in  BIT;
           CLR : in  BIT;
           Q : out  STD_LOGIC_VECTOR (7 downto 0));
end ring_counter;
 
architecture Behavioral of ring_counter is
 
begin
 
process(CLK,CLR)
	variable cmp	: 	INTEGER RANGE 0 TO 10;
	variable tmp	:	INTEGER RANGE 0 TO 7;
 
	begin
		if(CLR = '1') then
			tmp:=0;
			cmp:=0;
		elsif(CLK'EVENT AND CLK='1') then
			cmp:=cmp+1;
			if(cmp>=5) then
				cmp:=0;
				tmp:=tmp+1;
			end if;
		end if;
 
		case tmp is
			when	0	=> Q <= x"01";
			when	1	=>	Q <= x"02";
			when	2	=> Q <= x"04";
			when	3	=>	Q <= x"08";
			when	4	=> Q <= x"10";
			when	5	=> Q <= x"20";
			when	6	=> Q <= x"40";
			when	7	=> Q <= x"80";
			when 	OTHERS 	=> NULL;
		end case;
end process;
 
end Behavioral;
 
 

Using VHDL to design this circuit is very easy. If we don't prefer it we can design this ring counter digital circuit using schematic tool.

Register Transfer Level - RTL

We can look at its CPLD reports to know its resource usage.

CPLD Reports

After the design is succeed we need to assign its I/O pins using Floorplan IO.

Xilinx PACE

When we already assigned all I/O pins we need to save and close it. A user constraint ".ucf" will be generated by software.

#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "CLK"  LOC = "P5"  ;
NET "CLR"  LOC = "P25"  ;
NET "Q<0>"  LOC = "P40"  ;
NET "Q<1>"  LOC = "P39"  ;
NET "Q<2>"  LOC = "P38"  ;
NET "Q<3>"  LOC = "P37"  ;
NET "Q<4>"  LOC = "P36"  ;
NET "Q<5>"  LOC = "P35"  ;
NET "Q<6>"  LOC = "P34"  ;
NET "Q<7>"  LOC = "P33"  ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

We will need to re-run the Implement Design again to get CPLD ".jed" program file. We have to run the iMPACT tool to program the target CPLD device.

iMPACT

I use a parallel port JTAG cable "Parallel Cable III". The version of ISE Design is 14.7. It run on Windows 10 64-bit. Some of IBM type Desktop PC have a legacy parallel port. Click here to download the VHDL and user constraint file.