DIY Electronics Projects and Tutorials: XC9536 CPLD 7-Segment Up Down Counter Using VHDL

Overview

In this VHDL tutorial, I will design an up/down counter using VHDL code. Alternatively, we can use an ASIC 4516 and a 4511 chip to create this type of digital counter. However using a CPLD we can create and customize any digital circuit or ASIC by VHDL, Verilog code, or even schematic design tool.

XC9536 CPLD 7-Segment Up Down Counter Using VHDL

XC9536 CPLD Prototyping Board

I use my own XC9536 CPLD prototyping board to create this circuit design. It requires a little VHDL code, and half its macro-cells. Additionally, we can map its I/O device to any CPLD I/O pins.

VHDL Code

Its source code is very simple to write, I use one sequential block (process). The IF statement to make a frequency division, and to test digital logic input's state change. Additionally, the CASE Statement is used for decoding the output seven segments data. I added one active low reset signal to zero all variables.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:04:41 12/10/2023 
-- Design Name: 
-- Module Name:    counter_ud - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity counter_ud is
    Port ( RST : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           UP : in  STD_LOGIC;
           DOWN : in  STD_LOGIC;
           SSD : out  STD_LOGIC_VECTOR (7 downto 0));
end counter_ud;
 
architecture Behavioral of counter_ud is
 
begin
 
process(CLK, RST)
	variable	freq_count	:	INTEGER	RANGE	0	TO	29;
	variable	press_count	:	INTEGER	RANGE	0	TO	15;
 
	begin
		if(RST = '0')	then	freq_count:=0;	press_count:=0;
		elsif(CLK'event AND clk='1')	then
			freq_count:=freq_count+1;
			if(freq_count>20) then
				if(UP='0') then	
					press_count:=press_count+1;	freq_count:=0;	
				end if;
				if(DOWN='0') then	
					press_count:=press_count-1;	freq_count:=0;	
				end if;
			end if;
		end if;
		-- 7-Segment Display Process
		CASE press_count	IS
			WHEN	0	=>	SSD<=x"3F";
			WHEN	1	=>	SSD<=x"06";
			WHEN	2	=>	SSD<=x"5B";
			WHEN	3	=>	SSD<=x"4F";
			WHEN	4	=>	SSD<=x"66";
			WHEN	5	=>	SSD<=x"6D";
			WHEN	6	=>	SSD<=x"7D";
			WHEN	7	=>	SSD<=x"07";
			WHEN	8	=>	SSD<=x"7F";
			WHEN	9	=>	SSD<=x"6F";
			WHEN	10	=>	SSD<=x"77";
			WHEN	11	=>	SSD<=x"7C";
			WHEN	12	=>	SSD<=x"39";
			WHEN	13	=>	SSD<=x"5E";
			WHEN	14	=>	SSD<=x"79";
			WHEN	15	=>	SSD<=x"71";
			WHEN	OTHERS	=>	NULL;
		END CASE;
end process;
 
end Behavioral;

Up and Down logic input are active low. They are connected to pin 18 and 19 respectively. They are activated by pressing the buttons.

I/O Pin Assignments

I assign its I/O pins by using Xilinx PACE tool as follow.

Pin Assignments

A user constraints *.ucf file will be generated after we save the PACE.

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "CLK" LOC = "P5" ;
NET "DOWN" LOC = "P19" ;
NET "RST" LOC = "P25" ;
NET "SSD<0>" LOC = "P3" ;
NET "SSD<1>" LOC = "P4" ;
NET "SSD<2>" LOC = "P8" ;
NET "SSD<3>" LOC = "P9" ;
NET "SSD<4>" LOC = "P11" ;
NET "SSD<5>" LOC = "P13" ;

NET "SSD<6>" LOC = "P12" ;
NET "SSD<7>" LOC = "P7" ;
NET "UP" LOC = "P18" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

We can also create this source file and write the codes manually. After this step is completed, we will need to re-run the Implement Design to obtain its programming file *.jed .

Device Programming

We just run the iMPACT tool to program the target XC9536 CPLD. A high speed USB JTAG is popular now. However I still use a legacy parallel port JTAG header. It still present in Xilinx ISE Design Suite 14.7, and Microsoft Windows 10. My HP MT-6300 Desktop PC has a legacy PCI Express parallel port (LPT-25) card.