XC9536 CPLD LED Chasing Using VHDL

In this VHDL Example, I use ROL (Rotate Left) and ROR (Rotate Right) operators to chase the LEDs left or right. An input switch determines its chasing direction. A frequency divider is added to get a lower frequency driven from a NE555 square wave oscillator.

CPLD Hardware Test

VHDL source is quite simple due to the rotate operators.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:35:50 12/08/2023 
-- Design Name: 
-- Module Name:    LED_ROTATE - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity LED_ROTATE is
    Port ( CLK : in  STD_LOGIC;
           SEL : in  STD_LOGIC;
           LED : out BIT_VECTOR (7 downto 0));
end LED_ROTATE;
 
architecture Behavioral of LED_ROTATE is
 
signal tmp	:	BIT_VECTOR(7 DOWNTO 0) :=X"01";
 
begin
 
process(CLK,SEL)
	variable	count	:	INTEGER RANGE 0 TO 9;
	begin
		if(clk'event and clk = '1') then
			count:=count+1;
			if(count=9) then
				if(sel='0') then	tmp<=tmp ROL 1; 
				else	tmp<=tmp ROR 1; 
				end if;
			end if;
			LED<=tmp;
		end if;
end process;
end Behavioral;
 
 

I assign all the I/O pin as follow.

#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "CLK"  LOC = "P5"  ; 
NET "LED<0>"  LOC = "P40"  ; 
NET "LED<1>"  LOC = "P39"  ; 
NET "LED<2>"  LOC = "P38"  ; 
NET "LED<3>"  LOC = "P37"  ; 
NET "LED<4>"  LOC = "P36"  ; 
NET "LED<5>"  LOC = "P35"  ; 
NET "LED<6>"  LOC = "P34"  ; 
NET "LED<7>"  LOC = "P33"  ; 
NET "SEL"  LOC = "P25"  ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

Each I/O device are already placed on the XC9536 CPLD Test Board.

Its RTL schematic is shown below.

RTL

I use a Xilinx Parallel Cable III to program this CPLD.

iMPACT Device Programming Using Parallel Cable III

It still work on a Desktop PC operated by Microsoft Windows 10.

Click here to download its source file.